// Copyright (C) 1953-2023 NUDT
// Verilog module name - bufid_get   
// Version: V4.3.0.20230309
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         Descriptor Send
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps
 
module bufid_get 
(
        i_clk,
        i_rst_n,
        
        iv_ipv          ,       
        iv_inject_dbufid,
        i_desp_wr       ,
        
        i_pkt_bufid_wr,
        iv_pkt_bufid,
        o_pkt_bufid_ack,
        
        o_pkt_bufid_wr,
        ov_pkt_bufid,
        
        o_desp_wr,
        ov_desp 
        //ov_st_inject_dbufid 
    );

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;
//input
(*MARK_DEBUG="true"*)input       [2:0]       iv_ipv;
(*MARK_DEBUG="true"*)input       [4:0]       iv_inject_dbufid;
(*MARK_DEBUG="true"*)input                   i_desp_wr;

(*MARK_DEBUG="true"*)input                   i_pkt_bufid_wr;
(*MARK_DEBUG="true"*)input       [8:0]       iv_pkt_bufid;
(*MARK_DEBUG="true"*)output  reg             o_pkt_bufid_ack;
//output
(*MARK_DEBUG="true"*)output  reg             o_pkt_bufid_wr;
output  reg [8:0]       ov_pkt_bufid;

output  reg             o_desp_wr;
output  reg [16:0]      ov_desp;
//output  reg [4:0]       ov_st_inject_dbufid;
//temp ov_descriptor and ov_pkt for discarding pkt while the fifo_used_findows is over the threshold 
//internal wire&reg
     
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        o_pkt_bufid_ack       <= 1'b0;
        o_pkt_bufid_wr        <= 1'b0;
        ov_pkt_bufid          <= 9'b0; 
        
        o_desp_wr             <= 1'b0;
        ov_desp               <= 17'b0;
        //ov_st_inject_dbufid   <= 5'b0;
    end
    else begin
        if(i_pkt_bufid_wr == 1'b1 && i_desp_wr == 1'b1)begin//when descriptor come,pkt_bufid_wr have been already
            o_pkt_bufid_ack     <= 1'b1;
            
            o_pkt_bufid_wr      <= i_pkt_bufid_wr;
            ov_pkt_bufid        <= iv_pkt_bufid;
            
            ov_desp             <= {iv_inject_dbufid,iv_ipv,iv_pkt_bufid};
            //ov_st_inject_dbufid <= iv_inject_dbufid;
            o_desp_wr           <= 1'b1;
        end
        else if(i_pkt_bufid_wr == 1'b0 && i_desp_wr == 1'b1)begin
            o_pkt_bufid_ack     <= 1'b0;
            
            o_pkt_bufid_wr      <= 1'b0;
            ov_pkt_bufid        <= 9'b0;
            
            o_desp_wr          <= 1'b0;
            ov_desp            <= 17'b0;
            //ov_st_inject_dbufid   <= 5'b0;   
        end
        else begin
            o_pkt_bufid_ack       <= 1'b0;
                                  
            o_pkt_bufid_wr        <= 1'b0;
            ov_pkt_bufid          <= 9'b0;
            
            o_desp_wr             <= 1'b0;
            ov_desp               <= 17'b0;
            //ov_st_inject_dbufid   <= 5'b0;                  
        end
    end 
end
endmodule